1. Field of the Invention
The present invention relates, in general, to a method for forming a bump on a semiconductor device and, more particularly, to a method for forming a bump on a semiconductor device, advantageous in simplicity and permitting examination of the semiconductor device for defects in advance of the formation of the bump.
2. Description of the Prior Art
Recently, there have been developed a bare chip surface mounting method by which a semiconductor device is directly mounted on the surface of a substrate in a bare chip state thereof without packaging the semiconductor device. In general, on an aluminum pad of a semiconductor device, there is formed a bump for contacting with a substrate, which then serves as an intermediate to mount the semiconductor device on the surface of the substrate. Such semiconductor device mounted on the substrate in a bare chip state potentially has significant advantages over one in a package state, including shorter signal transfer path, better electrical characteristic and smaller size. These advantages enable an article including the mounted semiconductor device to be light, thin, compact and small.
In mounting a bare chip on the surface of a substrate, the following description for of a conventional formation processes for a bump on a semiconductor device, along with the problems generated therefrom, is given for better understanding of the background of the present invention, with reference to FIGS. 1A-1H.
FIGS. 1A through 1H, illustrates the conventional processes for forming a bump on an aluminum pad of a semiconductor device.
Firstly, on a predetermined portion of a semiconductor substrate 1, an aluminum pad 2, and a chrome (Cr), a copper (Cu) and a gold (Au) layers are formed, in due order, and subjected to an electroplating to form a ball limiting metallurgy (hereinafter, "BLM") layer 3 over the resulting structure, as shown in FIG. 1A.
On the entire upper surface of the BLM layer 3, there is laminated a photo resist layer 4 in a predetermined thickness, as shown in FIG. 1B.
Next, a photo resist removing region is defined over the photo resist layer 4 by using a metallic mask, as shown in FIG. 1C.
The metal mask is then subjected to an exposing and developing process, to remove the photo resist layer 4 and to open the photo resist above the aluminum pad 2. As a result, there appears a region where a bump is to be formed, as shown in FIG. 1D.
Thereafter, using an electroplating process, a bump (generally, solder) is deposited over the region, to form a bump having a predetermined thickness, as illustrated in FIG. 1E.
The remaining photo resist are is removed, as shown in FIG. 1F.
A chemical etching process is applied to the resulting structure, to remove unnecessary portions of the BLM layer 3, leaving the bump 5 atop the BLM layer 5 on the aluminum pad 2 formed on the substrate 1, as illustrated in FIG. 1G.
Finally, the bump 5 is re-flowed and changed into the form of a ball, as shown in FIG. 1H. Reference numeral 6 designates a passivation.
In the formation of a bump with the conventional method, as described above, a BLM layer is formed entirely over the semiconductor device and a bump is formed on a predetermined portion of the BLM layer. Beside the predetermined portion of the BLM, other portions, that is, the portions uncovered with the bump must be removed. For this purpose, an etching process is preceeded, but since it is intricate, an over etching or an under etching may occur between the solder and the BLM layer so that a crack is generated or the boundary of a bump is opened or shorted.
In addition, since testing of the semiconductor device is impossible in advance of the formation of the bump, it is not possible to detect defects of the semiconductor device until directly examining the semiconductor device.
Consequently, the conventional method for forming a bump on a semiconductor device, as illustrated above, is disadvantageous in the production yield and the productivity of semiconductor devices due to the inevitable BLM layer etching process and the impossibility of the pre-test.